Precise control over the impedance of output drivers is becoming an increasingly important factor in system designs, particularly those involving multiple integrated circuits (ICs) and one or more common buses. In such arrangements, it is typically important to match the impedance of a driver to the impedance of a transmission line in order to minimize signal reflections and preserve signal integrity.
An existing solution involves the basic approach of providing a replica circuit for sensing the value of an external (i.e., to the IC) resistor and enabling an appropriate number of fingers in the output driver pull-up (PU) and/or pull-down (PD) structures to match the on-chip driver impedance to an external impedance. FIG. 1 shows such a replica circuit where Rext 190 is the external calibrating resistor, C1 150 and C2 155 are comparators, and PU1 120 and PU2 130 are output pull-up structures implemented similarly. PU1 120 and PU2 130 each include multiple fingers and each finger has a p-type metal oxide semiconductor (pMOS) transistor in series with an on-chip resistor. Similarly, PD 140 includes multiple fingers. Each finger has an n-type metal oxide semiconductor (NMOS) transistor in series with an on-chip resistor. Vref 105 is a reference voltage generator that generates the voltage at which the impedance of the driver is to be matched. The control block 180 generates the clock and control signals to align various timings of the system. There are two feedback loops in the system: (1) a left loop comprised of comparator C1 150, n-bit up/down counter and register set 1 171, and PU1 120 and (2) a right loop comprised of comparator C2 155, up/down counter and register set 2 175, and PD 140.
Initially, the left loop can be enabled while the right loop is disabled. Every time the comparator C1 150 finds a difference in voltage on the positive and negative terminal of the comparator C1 150, the counter in the up/down counter and register set 1 171 is incremented or decremented accordingly, which in turn, turns off or on fingers in PU1 120. This process continues till the impedance of PU1 120 substantially equals Rext 190. The corresponding n-bit word can be stored in the register in the up/down counter and register set 1 171.
Once the PU1 120 array bits are stored in the register in the up/down counter and register set 1 171, the left loop may be disabled and the right loop enabled. By symmetry, the impedance of the PU2 130 is substantially the same as the impedance of PU1 120. The n-bit counter in the up/down counter and register set 2 175 is incremented or decremented so that the impedance of PD 140 becomes substantially equal to the impedance of PU2 130. The word indicating this final value can be stored in a register in the counter and register set 2 175.
FIG. 2 shows an associated output driver circuit 200. The associated output driver circuit 200 includes a PU1 212 structure and a PD 222 structure, which are substantially the same as PU1 120 and PD 140 in the replica circuit of FIG. 1. The signals PU<N:1> and PD<N:1> from the replica circuit of FIG. 1 are the inputs to the predriver stages Predrv (PU) 210 and Predrv (PD) 220, respectively, which enable the same number of fingers as determined in the corresponding replica PU1 120 or PD 140 of FIG. 1. The full n-bit conversion can be done at chip power up and minor re-calibration can be done again after powering up to accommodate for power supply or temperature changes.
However, the above approach has some drawbacks. One of the drawbacks is the dependence of the impedance of PU2 130 and PU1 120 on the input offset voltage of comparator C1 150 and another comparator C2 155 input offset in the loop on the right to calibrate the impedance of PD 140. This can introduce possibly two comparator input offset error components in the impedance determination of PD 140. Furthermore, the impedance of PU2 130, which serves as a reference for PD 140, relies on the matching between PU1 120 and PU2 130. In practice, there may be some sort of device mismatch between PU1 120 and PU2 130, including parasitic mismatch and resistor mismatch, and this can introduce another error factor in the PD 140 impedance determination.